Virtual direct memory access (DMA) channel technique with multiple engines for DMA controller
US8417842B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 16, 2008 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Dec 19, 2029 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A virtual DMA channel technique in which a generally larger number of DMA channels are mapped to a generally smaller number of DMA engines can provide a configuration in which switches amongst DMA engines (and therefore amongst a current working set of DMA channels currently mapped thereto) can be accomplished without context switch latency. Accordingly, as long as contents of the current working set can be appropriately managed, many changes (whether or nor priority based) between a current active DMA channel and a next runnable DMA channel can be accomplished without incurring a context switch latency such as normally associated with loading/restoring and/or saving DMA context information. In some embodiments, a working set or replacement strategy that seeks to cache a most frequently (or most recently) used subset of virtual DMA channels is employed. In some embodiments, a set- or frame-oriented variants of such strategies may be employed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.