Two partition accelerator and application of tiered flash to cache hierarchy in partition acceleration
US8417889B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 24, 2009 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Oct 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An approach is provided to identify a disabled processing core and an active processing core from a set of processing cores included in a processing node. Each of the processing cores is assigned a cache memory. The approach extends a memory map of the cache memory assigned to the active processing core to include the cache memory assigned to the disabled processing core. A first amount of data that is used by a first process is stored by the active processing core to the cache memory assigned to the active processing core. A second amount of data is stored by the active processing core to the cache memory assigned to the inactive processing core using the extended memory map.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.