Reconfigurable processor with designated processing elements and reserved portion of register file for interrupt processing
US8417918B2 · kind B2 · utility
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7References
12Claims
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Key dates
| Filing date | Feb 22, 2010 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Jun 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interrupt handling technology and a reconfigurable processor are provided. The reconfigurable processor includes a plurality of processing elements, and some of the processing elements are designated for interrupt handling. When an interrupt request occurs while the reconfigurable processor is executing a loop operation, the designated processing elements may process the interrupt request. The interrupt handling technology allows the interrupt request and the loop operation to be processed in parallel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.