Apparatus and method for implementing instruction support for performing a cyclic redundancy check (CRC)
US8417961B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2010 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Jun 30, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/0631
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques relating to a processor including instruction support for implementing a cyclic redundancy check (CRC) operation. The processor may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may include a cryptographic unit configured to receive instructions that include a first instance of a cyclic redundancy check (CRC) instruction defined within the ISA, where the first instance of the CRC instruction is executable by the cryptographic unit to perform a first CRC operation on a set of data that produces a checksum value. In one embodiment, the cryptographic unit is configured to generate the checksum value using a generator polynomial of 0x11EDC6F41. In some embodiments, the first instance of the CRC instruction specifies an initial value to be used in performing the first CRC operation, the set of data, and a storage location in which the cryptographic unit is configured to store the checksum value produced by the first CRC operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.