Patent · US Active

Dual clock first-in first-out (FIFO) memory system

US8417982B1 · kind B1 · utility

6Cited by
2References
20Claims
0Family size

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Inventors

Key dates

Filing dateAug 5, 2010
Grant dateApr 9, 2013
Priority date
Expiry dateOct 13, 2031

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F5/12
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Some of the embodiments of the present disclosure provide a method for operating a first in first out (FIFO) memory system in different clock domains, the method comprising receiving a write request in a first clock domain; generating, by a write shift and truncation module in response to receiving the write request, a shifted series of binary numbers such that the shifted series of binary numbers is a reduced sub-set of a first series of binary numbers; and generating, by a binary to Gray conversion module, a series of Gray code numbers corresponding to the shifted series of binary numbers. Other embodiments are also described and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.