Method and apparatus for camouflaging a standard cell based integrated circuit
US8418091B2 · kind B2 · utility
2Cited by
36References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2009 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Jul 11, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for camouflaging an application specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of interconnected functional logic is disclosed. The method adds functionally inert elements to the logical description or provides alternative definitions of standard logical cells to make it difficult for reverse engineering programs to be used to discover the circuit's function.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.