Method and system for design simplification through implication-based analysis
US8418093B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2009 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Apr 2, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems are provided for reducing an original circuit design into a simplified circuit design by merging gates that may not be equivalent but can be demonstrated to preserve target assertability with respect to the original circuitry design. A composite netlist is created from the simplified netlist and the original netlist. The composite netlist includes a number of targets that imply the existence of a target in the simplified netlist and a corresponding target in the original netlist. The implications are verified and then validated to ensure the simplified circuit design is a suitable replacement for the original circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.