Advisory system for verifying sensitive circuits in chip-design
US8418098B2 · kind B2 · utility
2Cited by
16References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2008 |
| Grant date | Apr 9, 2013 |
| Priority date | — |
| Expiry date | Mar 11, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A verification system for verifying an integrated circuit design is provided. The verification system includes a functional block finding module configured to identify potential sensitive circuits in the integrated circuit design; and a search module. The search module is configured to find sensitive circuits from the potential sensitive circuits; and verify the sensitive circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.