Parasitic vertical PNP bipolar transistor and its fabrication method in BiCMOS process

US8420475B2 · kind B2 · utility

Assignee

• SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD. · CN

Inventors

• Tzuyin CHIU · Shanghai, CN
• TungYuan Chu · Shanghai, CN
• Wensheng Qian · Shanghai, CN
• YungChieh Fan · Shanghai, CN
• Donghua Liu · Shanghai, CN
• Jun Hu · Shanghai, CN

Key dates

• Filing date: Dec 22, 2010
• Grant date: Apr 16, 2013
• Expiry date: Mar 24, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/177

Abstract

This invention published a parasitic vertical PNP bipolar transistor in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process; the bipolar transistor comprises a collector, a base and an emitter. Collector is formed by active region with p-type ion implanting layer. It connects a p-type buried layer which formed in the bottom region of STI (Shallow Trench Isolation). The collector terminal connection is through the p-type buried layer and the adjacent active region. The base is formed by active region with n type ion implanting which is on the collector. Its connection is through the original p-type epitaxy layer after converting to n-type. The emitter is formed by the p-type epitaxy layer on the base region with heavy p-type doped. This invention also comprises the fabrication method of this parasitic vertical PNP bipolar in BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) process. And this PNP bipolar transistor can be used as the IO (Input/Output) device in high speed, high current and power gain BiCMOS (Bipolar Complementary Metal Oxide Semiconductor) circuits. It also provides a device option with low cost.