MOS transistor and method for forming the same

US8420492B2 · kind B2 · utility

Assignee

• INSTITUTE OF MICROELECTRONICS OF THE CHINESE ACADEMY OF SCIENCES · CN

Inventors

• Huicai Zhong · San Jose, US
• Qingqing Liang · Fishkill, US
• Da Yang · San Diego, US
• Chao Zhao · Thuwal, SA

Key dates

• Filing date: Jan 27, 2011
• Grant date: Apr 16, 2013
• Expiry date: Feb 24, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

The invention provides a MOS transistor and a method for forming the MOS transistor. The MOS transistor includes a semiconductor substrate; a gate stack on the semiconductor substrate, and including a gate dielectric layer and a gate electrode on the semiconductor substrate in sequence; a source region and a drain region, respectively at sidewalls of the gate stack sidewalls of the gate stack and in the semiconductor; sacrificial metal spacers on sidewalls of the gate stack sidewalls of the gate stack, and having tensile stress or compressive stress. This invention scales down the equivalent oxide thickness, improves uniformity of device performance, raises carrier mobility and promotes device performance.