Parasitic vertical PNP bipolar transistor in BiCMOS process
US8421185B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 25, 2010 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Apr 18, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/177
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A parasitic vertical PNP device in one type of BiCMOS process with shallow trench isolation (STI) comprises a collector formed by a p type impurity ion implantation layer inside active area, the bottom of collector connects to a p type buried layer, the p type pseudo buried layer is formed in bottom of shallow trench at both sides of collector active region through ion implantation, deep contacts through field oxide to connect pseudo buried layers and to pick up the collector; a base, formed by n type impurity ion implantation layer which sits on top of above stated collector; an emitter, a p type epitaxy layer lies above base and is connected out directly by a metal contact. Part of the p type epitaxy layer is converted into n type, which serves as connection path of base. Present invented PNP can be used as output device of BiCMOS high frequency circuit. It has a small device area and conduction resistance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.