Integrated circuit device having through via and method for preparing the same
US8421193B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 18, 2010 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Jun 3, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device includes a bottom wafer, at least one stacking wafer positioned on the bottom wafer, and at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein the bottom wafer and the stacking wafer are bonded by an intervening adhesive layer, and no bump pad is positioned between the bottom wafer and the stacking wafer. A method for preparing an integrated circuit device includes the steps of forming a bottom wafer, forming at least one stacking wafer, bonding the at least one stacking wafer to the bottom wafer by an intervening adhesive layer, and forming at least one conductive via penetrating through the stacking wafer and into the bottom wafer in a substantially linear manner, wherein no bump pad is positioned between the bottom wafer and the stacking wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.