Wafer level semiconductor package and fabrication method thereof
US8421211B2 · kind B2 · utility
5Cited by
1References
13Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 27, 2010 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Sep 22, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A wafer level semiconductor package is provided. A warpage control barrier line formed in every package of a single wafer prevents wafer from warping. The changed shape of the interface between a semiconductor chip and a molding layer at the edge of the package disperses stress applied to the outside of the package, and suppress the generation and propagation of crack. The size of the package is reduced to that of the semiconductor, and the thickness of the package is minimized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.