Laminated and sintered ceramic circuit board, and semiconductor package including the circuit board
US8421215B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2011 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Dec 20, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/09827
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In the laminated and sintered ceramic circuit board according to the present invention, at least a portion of the inplane conductor is fine-lined, such that the shape of the cross-section surface of the fine-lined inplane conductor is trapezoid, and the height (a), the length (c) of the lower base and the length (d) of the upper base of the trapezoidal cross-section surfaces, and the interval (b) between the lower bases of the trapezoidal cross-section surfaces of the inplane conductors adjacent in a plane parallel to the principal surfaces of the board meet a certain relation. This provides a laminated ceramic circuit board with low open failure rate, short-circuit failure rate and high reliability against high temperature and high humidity in a downsized and short-in-height (thin) semiconductor package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.