Patent · US Active

Integrated circuit with stacked computational units and configurable through vias

US8421500B2 · kind B2 · utility

3Cited by

5References

23Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Harry Barowski · Balingen, DE
Tim Niggemeier · Laatzen, DE

Key dates

Filing date	Nov 23, 2010
Grant date	Apr 16, 2013
Priority date	—
Expiry date	Nov 23, 2030

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/14
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A technique for manufacturing a three-dimensional integrated circuit includes stacking a memory unit on a first die that includes a first computational unit. In this case, the memory unit is included in a second die. A second computational unit that is included in a third die is stacked on the second die. Sets of vertical vias that extend through the first, second, and third dies are connected to connect components of the first and second computational units and the memory unit. Multiplexers of the first and second computational units are configured to selectively couple the components to different ones of the sets of vertical vias responsive to respective control words for each of the first and third dies.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.