Multithreaded clustered microarchitecture with dynamic back-end assignment
US8423716B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2011 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Jul 15, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end and back-end units. A method may include measuring a performance metric of a back-end unit, comparing the measurement to a first value, and reassigning, or not, the back-end unit according to the comparison. Computer systems according to embodiments of the invention may include: a random access memory; a system bus; and a processor having a plurality of instruction caches, a plurality of front-end units each to process an individual thread from a corresponding one of the instruction caches; a plurality of back-end units; and an interconnect network coupled to the plurality of front-end units and the plurality of back-end units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.