Maintaining cache coherence in a multi-node, symmetric multiprocessing computer
US8423736B2 · kind B2 · utility
6Cited by
1References
18Claims
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Key dates
| Filing date | Jun 16, 2010 |
| Grant date | Apr 16, 2013 |
| Priority date | — |
| Expiry date | Oct 11, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Maintaining cache coherence in a multi-node, symmetric multiprocessing computer, the computer composed of a plurality of compute nodes, including, broadcasting upon a cache miss by a first compute node a request for a cache line; transmitting from each of the other compute nodes to all other nodes the state of the cache line on that node, including transmitting from any compute node having a correct copy to the first node the correct copy of the cache line; and updating by each node the state of the cache line in each node, in dependence upon one or more of the states of the cache line in all the nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.