Integrated circuit of decreased size
US8426973B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2009 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | May 24, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit including an insulating layer having first and second opposite surfaces. The circuit includes, in a first area, first conductive portions of a first conductive material, located in the insulating layer, flush with the first surface and continued by first vias of the first conductive material, of smaller cross-section and connecting the first conductive portions to the second surface. The circuit further includes, in a second area, second conductive portions of a second material different from the first conductive material and arranged on the first surface and second vias of the first conductive material, in contact with the second conductive portions and extending from the first surface to the second surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.