Bit scan circuits and method in non-volatile memory
US8427884B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2011 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Oct 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for counting in an N-bit string a number of bits M, having a first binary value includes N latch circuits in a daisy chain where each latch circuit has a tag bit that controls each to be either in a no-pass or pass state. Initially the tag bits are set according to the bits of the N-bit string where the first binary value corresponds to a no-pass state. A clock signal having a pulse train is run through the daisy chain to “interrogate” any no-pass latch circuits. It races right through any pass latch circuit. However, for a no-pass latch circuit, a leading pulse while being blocked also resets after a pulse period the tag bit from “no-pass” to “pass” state to allow subsequent pulses to pass. After all no-pass latch circuits have been reset, M is given by the number of missing pulses from the pulse train.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.