Memory device with internal signap processing unit
US8429493B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2008 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Apr 23, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1515
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for operating a memory (36) includes storing data in a plurality of analog memory cells (40) that are fabricated on a first semiconductor die by writing input storage values to a group of the analog memory cells. After storing the data, multiple output storage values are read from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets. The multiple output sets of the output storage values are preprocessed by circuitry (48) that is fabricated on the first semiconductor die, to produce preprocessed data. The preprocessed data is provided to a memory controller (28), which is fabricated on a second semiconductor die that is different from the first semiconductor die, so as to enable the memory controller to reconstruct the data responsively to the preprocessed data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.