System-level method for reducing power supply noise in an electronic system
US8429590B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2011 |
| Grant date | Apr 23, 2013 |
| Priority date | — |
| Expiry date | Jul 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a method for reducing power supply noise within an electronic system that includes an integrated circuit (IC), a package, and a printed circuit board (PCB) connected by a plurality of power delivery networks (PDN) is disclosed. Power supply noise within the system is reduced by defining a voltage compression limit for each PDN of the electronic system; determining a voltage compression for each PDN of the electronic system during a plurality of switching events; comparing the voltage compression of each PDN of the electronic system to the voltage compression limit for each switching event; and in response to the voltage compression of each PDN of the electronic system exceeding the limit, modifying the electronic system to reduce the voltage compression below the limit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.