Interconnection structure of three-dimensional semiconductor device
US8431969B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 2011 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Mar 10, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
Abstract
A three-dimensional semiconductor device includes stacked structures arranged two-dimensionally on a substrate, a first interconnection layer including first interconnections and disposed on the stacked structures, and a second interconnection layer including second interconnections and disposed on the first interconnection layer. Each of the stacked structures has a lower region including a plurality of stacked lower word lines, and an upper region including a plurality of stacked upper word lines disposed on the stack of lower word lines. Each of the first interconnections is connected to one of the lower word lines and each of the second interconnections is connected to one of the upper word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.