Integrated circuits with edge-adjacent devices having reactance values
US8431970B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2010 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Apr 9, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit has a plurality of terminals for making electrical connection to the integrated circuit. At least one device is formed adjacent an outer edge of the integrated circuit. The device includes at least one metal conductor for forming an edge seal for protecting the integrated circuit during die singulation. The device is coupled to one or more functional circuits within the integrated circuit by routing the at least one metal conductor to the one or more functional circuits, the at least one device providing a reactance value to the one or more functional circuits for non-test operational use. The device may be formed as one or more capacitors or as one or more inductors. Various structures may be used for the capacitor and the inductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.