Patent · US Active

Chip package and fabrication method thereof

US8432032B2 · kind B2 · utility

2Cited by

1References

24Claims

0Family size

Inventors

Chia-Sheng Lin · Taoyuan, TW
Chia-Lun Tsai · Hsinchu, TW
Chang-Sheng Hsu · Hsinchu, TW
Po-Han Lee · Taipei, TW

Key dates

Filing date	Jan 13, 2010
Grant date	Apr 30, 2013
Priority date	—
Expiry date	May 10, 2031

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/1461
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposite second surface. A through hole is formed on the first surface, extending from the first surface to the second surface. A conductive trace layer is formed on the first surface and in the through hole. A buffer plug is formed in the through hole and a protection layer is formed over the first surface and in the through hole.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.