Phase-locked loop (PLL) circuit
US8432201B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2012 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | May 19, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/093
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase-locked loop (PLL) generates an oscillator signal based on an input reference signal. A voltage-to-current oscillator converts generates the oscillator signal based on a control. A charge pump circuit generates the charge pump current based on an error (feedback) signal. A low pass filter generates the control voltage based on the charge pump current. A capacitor is connected to an input terminal of the low pass filter that is charged to a voltage level of the control voltage by the low pass filter when the PLL is switched OFF. The voltage across the capacitor is buffered and fed back to the low pass filter when the PLL is switched ON, to reduce time taken by the VCO to generate the oscillator signal. The PLL is used in an electronic circuit to reduce the wake-up time of the electronic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.