Digital locked loops and methods with configurable operating parameters
US8432202B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 30, 2012 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | May 30, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/091
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A locked loop may have an adjustable hysteresis and/or a tracking speed that can be programmed by a user of an electronic device containing the locked loop or controlled by an integrated circuit device containing the locked loop during operation of the device. The looked loop may include a phase detector having a variable hysteresis, which may be coupled to receive a reference clock signal and an output clock signal from a phase adjustment circuit through respective frequency dividers that can vary the rate at which the phase detector compares the phase of the output clock signal to the phase of the reference clock signal, thus varying the tracking speed of the loop. The hysteresis and tracking speed of the locked loop may be programmed using a variety of means, such as by a temperature sensor for the electronic device, a mode register, a memory device command decoder, etc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.