Delay lock loop system with a self-tracking function and method thereof
US8432206B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 2012 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Mar 20, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay lock loop system includes a timing controller, an OR gate, an input buffer, a pulse generator, and a delay lock loop. The timing controller is used for outputting an external enable signal periodically while a power saving signal is at a logic-low voltage, and being disabled according to a logic-high voltage of the power saving signal. The pulse generator is used for generating a pulse according to the positive edge of the power saving signal. The OR gate is coupled to the timing controller for receiving the power saving signal, the pulse, and the external enable signal, and outputting an enable signal according to the power saving signal and the external enable signal. The delay lock loop is coupled to the OR gate and the input buffer for enabling the delay lock loop again according to the enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.