Method for power reduction and a device having power reduction capabilities
US8432209B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 14, 2009 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | May 14, 2029 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/012
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A device that includes a dual edge triggered flip-flop that has state retention capabilities, the dual edge triggered flip-flop includes: a retention latch that includes a first inverter, a second inverter and a first transfer gate; wherein the first and second inverters receive power during a power gating period; a second latch that includes a third inverter, a fourth inverter and a second transfer gate; wherein the third and fourth inverters are powered down during a power gating period; a third transfer gate that is coupled between input nodes of the retention latch and the second latch; wherein the third transfer gate is opened during the power gating period; wherein the first transfer gate is controlled by a control signal and the second transfer gate is controlled by an inverted control signal; wherein the retention latch stores, at the end of the power gating period a retention value; wherein the retention value is selected, in response to a value of the control signal when the power gating period starts, out of a first initial value stored at the retention latch at the beginning of the power gating period and a second initial value stored at the second latch at the beginnin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.