Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor
US8433850B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2008 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Jul 3, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for instruction restarts and inclusion in processor micro-op caches are disclosed. Embodiments of micro-op caches have way storage fields to record the instruction-cache ways storing corresponding macroinstructions. Instruction-cache in-use indications associated with the instruction-cache lines storing the instructions are updated upon micro-op cache hits. In-use indications can be located using the recorded instruction-cache ways in micro-op cache lines. Victim-cache deallocation micro-ops are enqueued in a micro-op queue after micro-op cache miss synchronizations, responsive to evictions from the instruction-cache into a victim-cache. Inclusion logic also locates and evicts micro-op cache lines corresponding to the recorded instruction-cache ways, responsive to evictions from the instruction-cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.