Ron Gabor
63Patents
6h-index
107Co-inventors
71Inventor score
Filing activity: Aug 3, 2005 → Apr 18, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9652375B2 | Multiple chunk support for memory corruption detection architectures | Physics | 13 | Active |
| US10162694B2 | Hardware apparatuses and methods for memory corruption detection | Physics | 11 | Active |
| US9619313B2 | Memory write protection for memory corruption detection architectures | Physics | 11 | Active |
| US9858140B2 | Memory corruption detection | Physics | 10 | Active |
| US7725745B2 | Power aware software pipelining for hardware accelerators | Physics | 10 | Active |
| US7827551B2 | Real-time threading service for partitioned multiprocessor systems | Physics | 7 | Active |
| US9672019B2 | Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads | Physics | 6 | Active |
| US8782374B2 | Method and apparatus for inclusion of TLB entries in a micro-op cache of a processor | Emerging Cross-Sectional Technologies | 6 | Active |
| US8103831B2 | Efficient method and apparatus for employing a micro-op cache in a processor | Emerging Cross-Sectional Technologies | 6 | Active |
| US8706979B2 | Code reuse and locality hinting | Emerging Cross-Sectional Technologies | 5 | Active |
| US9003421B2 | Acceleration threads on idle OS-visible thread execution units | Physics | 4 | Active |
| US8543796B2 | Optimizing performance of instructions based on sequence detection or information associated with the instructions | Physics | 3 | Active |
| US7437546B2 | Multiple, cooperating operating systems (OS) platform system and method | Physics | 3 | Active |
| US10073727B2 | Heap management for memory corruption detection | Physics | 3 | Active |
| US10725755B2 | Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads | Physics | 3 | Active |
| US8127085B2 | Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor | Emerging Cross-Sectional Technologies | 3 | Active |
| US10095573B2 | Byte level granularity buffer overflow detection for memory corruption detection architectures | Physics | 2 | Active |
| US9229524B2 | Performing local power gating in a processor | Emerging Cross-Sectional Technologies | 2 | Active |
| US8433850B2 | Method and apparatus for pipeline inclusion and instruction restarts in a micro-op cache of a processor | Emerging Cross-Sectional Technologies | 2 | Active |
| US8909988B2 | Recoverable parity and residue error | Physics | 2 | Active |
| US9690591B2 | System and method for fusing instructions queued during a time window defined by a delay counter | Emerging Cross-Sectional Technologies | 2 | Active |
| US8935514B2 | Optimizing performance of instructions based on sequence detection or information associated with the instructions | Physics | 1 | Active |
| US9934164B2 | Memory write protection for memory corruption detection architectures | Physics | 1 | Active |
| US8166320B2 | Power aware software pipelining for hardware accelerators | Physics | 1 | Active |
| US10802567B2 | Performing local power gating in a processor | Emerging Cross-Sectional Technologies | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.