Clock-reconvergence pessimism removal in hierarchical static timing analysis
US8434040B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 27, 2011 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Apr 27, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and a method are disclosed for performing clock re-convergence pessimism removal (CRPR) during hierarchical static timing analysis (HSTA). A clock network is divided into a plurality of blocks. A top level includes clock components not included in the plurality of blocks. Block level analysis is performed to determine timing information for each of the plurality of blocks. If available, CRPR data from top level analysis is accounted for in block level analysis. Subsequently, similar analysis is performed on components that are included in top level analysis. If available, CRPR data from bottom level analysis is accounted for in top level analysis. CRPR data can be requested during levels of analysis from the other level. These steps are repeated until analysis is complete.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.