Specifying placement and routing constraints for security and redundancy
US8434044B1 · kind B1 · utility
2Cited by
2References
19Claims
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Assignee
Inventors
Key dates
| Filing date | Dec 14, 2010 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Jan 31, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable chip design tool is provided to enumerate and specify the security and/or redundancy constraints of a programmable chip design. A design is implemented with a high-level security or redundancy scheme, and the programmable chip design tool applies the scheme while simultaneously optimizing for desired metrics (logic density, routability, timing, power, etc.). An underlying assignment scheme as well as user interface components used to enter this assignment scheme are provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.