Register allocation with SIMD architecture using write masks
US8434074B2 · kind B2 · utility
19Cited by
3References
14Claims
0Family size
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Key dates
| Filing date | Feb 24, 2010 |
| Grant date | Apr 30, 2013 |
| Priority date | — |
| Expiry date | Oct 18, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single instruction multiple data processor may accomplish register allocation by identifying live ranges that have incompatible write masks during compilation. Then, edges are added in an interference graph between live ranges that have incompatible masks so that those live ranges will not be assigned to the same physical register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.