Method of forming a CMOS IC having a compressively stressed metal layer in the NMOS area
US8435849B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 5, 2012 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Apr 5, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gate stack for an NMOS transistor in an IC to induce tensile stress in the NMOS channel is disclosed. The gate stack includes a first layer of undoped polysilicon, a second layer of n-type polysilicon to establish a desired work function in the gate, layer of compressively stressed metal, and a third layer of polysilicon to provide a silicon surface for subsequent formation of metal silicide. Candidates for the compressively stressed metal are TiN, TaN, W, and Mo. In a CMOS IC, the n-type polysilicon layer and metal layer are patterned in NMOS transistor areas, while the first polysilicon layer and third polysilicon layer are patterned in both NMOS and PMOS transistor areas. Polysilicon CMP may be used to reduce topography between the NMOS and PMOS gate stacks to facilitate gate pattern photolithography.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.