Fan-out wafer level package with polymeric layer for high reliability
US8436255B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 31, 2009 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Dec 12, 2030 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49117
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A polymeric layer encompassing the solder elements of a ball grid array in an electronics package. The polymeric layer reinforces the solder bond at the solder ball-component interface by encasing the elements of the ball grid array in a rigid polymer layer that is adhered to the package structure. Stress applied to the package through the ball grid array is transmitted to the package structure through the polymeric layer, bypassing the solder joint and improving mechanical and electrical circuit reliability. In one embodiment of a method for making the polymeric layer, solder elements bonded to external pads on a structure of the package are submerged in a fluidic form of the polymeric layer. The fluidic form is solidified and then a portion of the resulting polymeric layer is removed to make the solder elements accessible for mounting the package to a printed circuit board or other external circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.