Semiconductor wafer having test modules including pin matrix selectable test devices
US8436635B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 1, 2009 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Mar 16, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2831
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor wafer includes a plurality of die areas including circuit elements, and at least one test module (TM) on the wafer outside the die areas. The TMs include a test circuit including plurality of test transistors arranged in a plurality of rows and columns. The plurality of test transistors include at least three terminals (G, S, D and B). The TMs each include a plurality of pads. The pads include a first plurality of locally shared first pads each coupled to respective ones of a first of the three terminals, a second plurality of locally shared second pads each coupled to respective ones of a second of the three terminals, and at least one of the plurality of pads coupled to a third of the three terminals. The TM provides at least 2 pin transistor selection for uniquely selecting from the plurality of test transistors for testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.