Memory cell employing reduced voltage
US8437214B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2012 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Jul 17, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/413
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory array has a memory cell that comprises a storage element storing a logical state at a reduced voltage during at least one functional operation and a write access circuit configured to connect the storage element to at least a first write bit line in response to a write signal on the write word line for writing the logical state to the memory cell. The memory cell further comprises a read access circuit including an input node connected to the storage element and an output node connected to a read bit line of the memory array. The read access circuit is enabled and configured to read the logic state of the storage element in response to a read signal on the read word line. The reduced voltage is reduced relative to an operating voltage of at least one peripheral circuit associated with reading and/or writing of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.