Memory with word-line segment access
US8437215B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 20, 2011 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Jul 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory comprises a row of bit cells, including a first plurality of bit cells and a second plurality of bit cells. A first word line segment driver is connected to the first plurality of bits cells. A second word line segment driver is connected to the second plurality of bits cells. The first and second word line segment drivers are selectively operable for activating one of the first and second pluralities of bit cells at a time to the exclusion of the other plurality of bit cells. A shared sense amplifier is coupled to at least one of the first plurality of bit cells and at least one of the second plurality of bit cells. The shared sense amplifier is configured to receive signals from whichever of the one first or second bit cell is activated by its respective word line segment driver at a given time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.