Apparatus and methods for on layer concurrency in an integrated circuit
US8438306B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 2, 2010 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Jun 2, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7825
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, and system for providing layer concurrency connecting two or more master Intellectual Property cores to a Network on a Chip (NoC) for an integrated circuit is provided. An embodiment includes two masters connected using a common tightly coupled protocol to a first interface of an NoC. A protocol conversion unit can be coupled between the two or more masters and the NoC to convert a request in the tightly coupled protocol to a decoupled protocol that decouples request phasing from response phasing and then passes the request in the decoupled protocol format onto the NoC. The system also provides for arbitration amongst the two or more masters. Requests from the masters are still in the common tightly coupled protocol and are translated by the protocol conversion unit into a request in a decoupled protocol to enable out of order return of responses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.