Structures and control processes for efficient generation of different test clocking sequences, controls and other test signals in scan designs with multiple partitions, and devices, systems and processes of making
US8438437B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2010 |
| Grant date | May 7, 2013 |
| Priority date | — |
| Expiry date | Nov 19, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318547
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A scannable integrated circuit (100) including a functional integrated circuit (P1, P2) having scan chains, multiple scan decompressors (120.1, 120.2), each operable to supply scan bits to some of the scan chains (101.k, 102.k), a shared scan-programmable control circuit (110, 300), a tree circuit (400) coupled with the functional integrated circuit (P1, P2), the shared scan-programmable control circuit (110, 300) coupled to control the tree circuit (400), and a selective coupling circuit (180) operable to provide selective coupling with the shared scan-programmable control circuit (110, 300) for scan programming through any of the multiple scan decompressors (120.1, 120.2). Other circuits, devices, systems, and processes of operation and manufacture are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.