Schemes for forming barrier layers for copper in interconnect structures
US8440564B2 · kind B2 · utility
9Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2012 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Jul 17, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor structure includes providing a substrate; forming a low-k dielectric layer over the substrate; embedding a conductive wiring into the low-k dielectric layer; and thermal soaking the conductive wiring in a carbon-containing silane-based chemical to form a barrier layer on the conductive wiring. A lining barrier layer is formed in the opening for embedding the conductive wiring. The lining barrier layer may comprise same materials as the barrier layer, and the lining barrier layer may be recessed before forming the barrier layer and may contain a metal that can be silicided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.