Semiconductor device including SiON gate dielectric with portions having different nitrogen concentrations
US8441078B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 2010 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Oct 20, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) includes a substrate having a top semiconductor surface including at least one MOS device including a source and a drain region spaced apart to define a channel region. A SiON gate dielectric layer that has a plurality of different N concentration portions is formed on the top semiconductor surface. A gate electrode is on the SiON layer. The plurality of different N concentration portions include (i) a bottom portion extending to the semiconductor interface having an average N concentration of <2 atomic %, (ii) a bulk portion having an average N concentration >10 atomic %, and (iii) a top portion on the bulk portion extending to a gate electrode interface having an average N concentration that is ≧2 atomic % less than a peak N concentration of the bulk portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.