Strain-compensating fill patterns for controlling semiconductor chip package interactions
US8441131B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 12, 2011 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Sep 12, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Generally, the subject matter disclosed herein relates to sophisticated semiconductor chips that may be less susceptible to the occurrence of white bumps during semiconductor chip packaging operations, such as flip-chip or 3D-chip assembly, and the like. One illustrative semiconductor chip disclosed herein includes, among other things, a bond pad and a metallization layer below the bond pad, wherein the metallization layer is made up of a bond pad area below the bond pad and a field area surrounding the bond pad area. Additionally, the semiconductor device also includes a plurality of device features in the metallization layer, wherein the plurality of device features has a first feature density in the bond pad area and a second feature density in the field area that is less than the first feature density.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.