Bandwidth compression for shader engine store operations
US8441487B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 30, 2007 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | May 12, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T9/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention set forth systems and methods for compressing thread group data written to frame buffer memory to increase overall memory performance. A compression/decompression engine within the frame buffer memory interface includes logic configured to identify situations where the threads of a thread group are writing similar scalar values to memory. Upon recognizing such a situation, the engine is configured to compress the scalar data into a form that allows all of the scalar data to be written to or read from the frame buffer memory in fewer clock cycles than would be required to transmit the data in uncompressed form to or from memory. Consequently, the disclosed systems and methods are able to effectively increase memory performance when executing thread group STORE and LOAD operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.