Sector array addressing for ECC management
US8441836B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 2010 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Feb 1, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0023
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An addressing scheme for non-volatile memory arrays having short circuit defects that manages the demand for error correction. The scheme generally avoids simultaneous active driving of the row line and column line of the selected cell during write. Instead, only a single row or column line is actively driven at any one time and all other array lines are left floating. In addition, the number of memory cells accessed from a given row or column during a fetch may be limited. The benefits of the scheme include preventing short circuits from drawing excess currents through the array and limiting the frequency of read or write failures caused by short circuits to a manageable number. In one embodiment, the scheme maintains the demand for error correction to within the error correction capability of a flash controller. Exemplary embodiments include phase-change memory arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.