Patent · US Active

Memory device with robust write assist

US8441874B2 · kind B2 · utility

26Cited by

3References

22Claims

0Family size

Assignee

STMicroelectronics International N.V. · NL

Inventors

Rakesh Sinha · Cupertino, US
Dhori Kedar Janardan · Mahesana, IN
Sachin Gulyani · Delhi, IN

Key dates

Filing date	Dec 28, 2010
Grant date	May 14, 2013
Priority date	—
Expiry date	Mar 27, 2031

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/413
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to disable the supply of charge and couple the write enable circuit to at least one of the pair of bit lines after a first determined period following the reception of the write signal.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.