Method and apparatus for implementing a data bus interface
US8443129B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2010 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Oct 4, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data bus interface channel controller circuit for an N-bit data bus is described. A FIFO command queue is coupled to receive and buffer one or more commands formatted for M-bit transactions. A FIFO data queue is coupled to receive and buffer N-bit formatted data packets. A first translation circuit is coupled to the FIFO command queue and configured to translate the each commands into a selected one of a plurality of transaction formats. A transmission control circuit is coupled and configured to receive and transmit commands removed from the FIFO command queue. The transmission control circuit is configured to track a number of outstanding transmitted commands and, in response to receiving a command having a transaction format different from the previously received command, delay transmission of commands on the N-bit data bus until the number of outstanding transmitted commands equals zero.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.