Hardware automatic performance state transitions in system on processor sleep and wake events
US8443216B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2012 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Aug 21, 2032 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.