Error correction in copy back memory operations
US8443260B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2007 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | May 14, 2031 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1064
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of storage and retrieval of data in a flash memory system, the flash memory system comprising a cache storage area of relatively high reliability, and a main storage area of relatively low reliability, the method comprising adding to data a level of error correction redundancy higher by a predetermined margin than that required for the cache storage area, writing the data to the cache storage area, and from the cache storage area copying the data directly to the main storage area, the predetermined margin being such as to allow subsequent error correction to compensate for errors accumulated from the cache storage area and the main storage area. In this way the memory die copy back operation can be used for copying the data from the cache to the main memory and two out of four transfers over the data bus to the flash controller are avoided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.