Pessimism removal in the modeling of simultaneous switching noise
US8443321B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2008 |
| Grant date | May 14, 2013 |
| Priority date | — |
| Expiry date | Oct 1, 2030 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for determining induced noise on a given victim by a set of aggressor signals are presented, and for identifying the worst case aggressor switching time alignment that causes the worst case victim noise. The method removes circuit analysis pessimism related to simultaneous switching noise (SSN) in a circuit design tool by determining physically impossible combinations of victim-aggressor input/output (I/O) pins in a circuit design and culling out the impossible combinations from the list of possible victim-aggressor combinations. The method further performs a switching window SSN analysis of the circuit design with a common uncertainty removal algorithm taking into consideration the list of possible victim-aggressor combinations, and determines the maximum voltage noise induced on I/O pins of the circuit design. The results of the noise analysis are displayed to the user.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.